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New family of boost switched-capacitor seven-level inverters (BSC7LI)
  • Lee, Sze Sing ;
  • Bak, Yeongsu ;
  • Kim, Seok Min ;
  • Joseph, Anto ;
  • Lee, Kyo Beum
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Publication Year
2019-11-01
Publisher
Institute of Electrical and Electronics Engineers Inc.
Citation
IEEE Transactions on Power Electronics, Vol.34, pp.10471-10479
Keyword
Boost inverterinverter topologymultilevel inverter (MLI)switched-capacitor
Mesh Keyword
Boost invertersCapacitor voltage balancingDirect current voltageHigher output voltagesInverter topologiesMulti Level Inverter (MLI)Multilevel inverter topologySwitched capacitor
All Science Classification Codes (ASJC)
Electrical and Electronic Engineering
Abstract
This paper proposes a new family of multilevel inverter topology that is able to generate seven voltage levels by utilizing one or two floating capacitors and 10 power switches. This novel boost switched-capacitor seven-level inverter possesses voltage boosting capability with an achievable maximum voltage level 1.5 times the input direct current (dc) voltage. The generation of higher output voltage does not incur high-voltage stress on any power switch in this topology, as the peak inverse voltages of all power switches do not exceed the input source voltage. In addition, capacitor voltage balancing is not essential since the floating capacitors are effectively balanced during the charging and discharging processes. Furthermore, the proposed topology eliminates the need for multiple isolated dc sources, and a single dc source is sufficient in both its single-phase and three-phase topologies. The operating principle and steady-state analysis of the proposed topology are elaborated. Experimental results from a single-phase prototype are then presented to verify the validity of the proposed topology.
Language
eng
URI
https://dspace.ajou.ac.kr/dev/handle/2018.oak/30913
DOI
https://doi.org/10.1109/tpel.2019.2896606
Fulltext

Type
Article
Funding
Manuscript received October 30, 2018; revised December 19, 2018; accepted January 26, 2019. Date of publication January 31, 2019; date of current version August 29, 2019. This work was supported in part by the KEPCO Research Institute under the project entitled \u201cDesign of analysis model and optimal voltage for MVDC distribution system\u201d (R17DA10), in part by the Korea Foundation for Advanced Studies under 2018\u201319 International Scholar Exchange Fellowship, and in part by the Malaysian Ministry of Higher Education under Fundamental Research Grant Scheme (FRGS/1/2018/TK04/USMC/02/1). Recommended for publication by Associate Editor E. Babaei. (Corresponding author: Kyo-Beum Lee.) S. S. Lee is with the Department of Electronics and Computer Science, University of Southampton Malaysia, Johor Bahru 79200, Malaysia, and also with the Power Electronics Laboratory, Ajou University, Suwon 16499, South Korea (e-mail:,szesinglee@gmail.com).
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