Artificial intelligence (AI)-based consumer electronic (CE) devices generate massive amounts of accumulated hot data. Persisting this data into such devices' storage media like the universal flash storage (USF) becomes an issue for flash storage system to manage hot data optimally. Consequently, efforts have been made to support many CE applications and achieve high performance and scalability storage in CE devices. However, it is challenging to find a compatible flash translation layer (FTL) for such flash devices, which can efficiently handle frequent updates imposed by the incoming hot data. Moreover, FTL should be able to handle the hot multimedia data that induces cache-miss penalties which in-turn degrades our flash storage performance. This paper proposes a hybrid flash device for fast address translations called HyFAT which is workload-compatible. HyFAT improves device performance and efficiently manages the combined QuadLevel cell (QLC) for data storage and scalability with SingleLevel cell (SLC) for fast mapping entry storage. The experimental results with realistic workloads show that our approach can improve device performance throughput by 18% on average, compared to traditional DFTL and RFTL.
Manuscript received September 14, 2018; revised December 18, 2018 and February 18, 2019; accepted February 26, 2019. Date of publication March 11, 2019; date of current version April 23, 2019. This work was supported by the Basic Science Research through the National Research Foundation of Korea (NRF) funded by the Ministry of Education under Grant NRF-2016R1D1A1BO3934129 and Grant NRF-2017R1D1A3B04031440. (Corresponding author: Tae-Sun Chung.) R. Mativenga and T.-S. Chung are with the Department of Computer Engineering, Ajou University, Suwon 443-749, South Korea (e-mail: ronniematie@ajou.ac.kr; tschung@ajou.ac.kr).
