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DC-link Ripple Reduction in a DPWM-Based Two-Level VSIoa mark
  • Tcai, Anatolii ;
  • Alsofyani, Ibrahim Mohd ;
  • Seo, In Yong ;
  • Lee, Kyo Beum
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Publication Year
2018-11-01
Publisher
MDPI AG
Citation
Energies, Vol.11
Keyword
CapacitorDc-linkRippleVoltage source inverter
Mesh Keyword
DC linksDiscontinuous pulse width modulations (DPWM)Efficiency and reliabilityParallel connectionsPhase shift techniquesRippleVoltage source inverterVoltage Source Inverter (VSI)
All Science Classification Codes (ASJC)
Renewable Energy, Sustainability and the EnvironmentEnergy Engineering and Power TechnologyEnergy (miscellaneous)Control and OptimizationElectrical and Electronic Engineering
Abstract
This paper proposes a new method to reduce the ripple current of the DC-link capacitor in a two-level voltage source inverter (VSI), with a discontinuous pulse-width modulation (DPWM). In real applications, a capacitor block is very bulky, due to the parallel connection of several capacitors that share the value of the ripple current. Hence, it contributes significantly to the volume and weight of the whole system. Conventional DPWM is used to minimize the amount of switching for the power transistors, therefore, reducing stress and power loss. This leads to increased efficiency and reliability of the system. Nevertheless, the reduction of the DC link ripple current is still not optimal. Therefore, the proposed method introduces a PWM phase-shift technique to provide further reduction of the DC-link ripple current in a DPWM-based VSI. The efficacy of the proposed method is confirmed by simulation and experimental results.
ISSN
1996-1073
Language
eng
URI
https://dspace.ajou.ac.kr/dev/handle/2018.oak/30490
DOI
https://doi.org/10.3390/en11113008
Fulltext

Type
Article
Funding
Funding: This research was funded in part by \u201cHuman Resources Program in Energy Technology\u201d of Korea Institute of Energy Technology Evaluation and Planning (KETEP), granted financial resource from the Ministry of Trade, Industry & Energy, Republic of Korea. (No. 20174030201660) and in part by KEPCO Research Institute under the project \u201cDesign of analysis model and optimal voltage for MVDC distribution system (R17DA10)\u201d.
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