DC-Link ripple current reduction method for three-level inverters with optimal switching pattern

Abstract

This paper presents an optimized switching strategy to reduce the dc-link ripple current for three-level photovoltaic (PV) inverters. The large electrolytic capacitors are commonly used for the dc link of power electronics applications to stabilize the dc-link voltage. The most important factor of designing the dc-link capacitor is the allowable current ripple. The over-ripple current flowing through the capacitor causes a high heat loss, shortened lifespan, low stability, and reliability. The proposed switching scheme selects voltage vectors and reconfigures dwelling order of the vectors to reduce the capacitor ripple current. This switching method is able to extend the lifetime of the dc-link capacitors by simple software programming. In addition, this switching method reduces the common-mode voltage and leakage current that represent high reliability and safety of the system. The effectiveness of the proposed method is verified with simulations and experimental results.