The successive cancellation list (SCL) decoding algorithm has been proposed to
<br>enhance error correction in successive cancellation (SC) decoders for polar codes.
<br>However, implementing SCL decoding in hardware requires multiple SC cores,
<br>which leads to increased hardware complexity, power consumption, and
<br>computational complexity. In this thesis, we propose a power-efficient SCL
<br>decoding architecture that utilize power gating techniques to address these issues.
<br>The proposed power gating-based SCL decoder architecture operates in the
<br>following two scenarios. The first scenario involves shutting off a subset of the
<br>decoding cores for the entire decoding process, using power gating. This approach
<br>significantly reduces computational complexity by up to 75% in low noise
<br>environments. The second scenario achieves low power consumption by
<br>selectively shutting off some decoding cores during specific parts of the decoding
<br>process. This method results in up to 19% of reduction in computational complexity.
<br>The proposed architecture and scenarios are also evaluated in terms of error
<br>correction performance, measured by the frame error rate (FER). The two scenarios
<br>in which the proposed architecture operates provide us with a wider range of
<br>performance options that span from a conventional SCL with a list size of L−M to
<br>a conventional SCL with a list size of L.
