Advanced error correction codes (LDPC, Polar, etc.) theoretically have performance close to Shannon's limit. However, there is a performance degradation at the implementation stage. To be a good error correction code, various factors such as low computational complexity and ease of implementation must be met while satisfying good error correction ability.
The author claims that the advanced error correction code not only satisfies the theoretically high error correction performance but also, in fact, it is most important to implement a low power error correction code decoder. This thesis discusses low-power algorithms and implementations for LDPC code, Polar code, and BCH code.
Since LDPC codes have a characteristic of iterative decoding algorithm, an adaptive forced convergence algorithm is proposed that is deactivated when a variable node exceeds the threshold value. The proposed forced convergence algorithm was able to further reduce the check node computation amount by approximately 66.86% and 35.68%.
In Polar code, as the size of L increases in the SCL decoding algorithm, the Path metric sorting time increases exponentially. In order to achieve high throughput and low latency of Polar list decoder, the proposed L minimum value generator using bit-serial scheme to support high operating frequency of Polar list decoder at high list size. Since the ratio of the area corresponding to the controller is high when the list size is small, the proposed generator has a slightly higher AT complexity compared to previous ones. However, when L = 16 and L = 32, the proposed L minimum value generator can be performed with AT complexity of 39% and 11.5% compared to previous ones.
The proposed BCH decoder for low-power medical devices adopts an early termination technique, reducing the power and latency of Syndrome computation and Chien search module by 42.08% and 45.78%, respectively. The proposed BCH decoder uses the Peterson algorithm considering power and area for wireless capsule endoscopy.
