Successive-cancellation list (SCL) is a decoding algorithm for polar codes that require high latency owing to serial operations. While several algorithms have been proposed to improve this latency with additional circuits, the area was enlarged. In this paper, we propose a fast multibit decision method with small area based SCL decoding algorithm. First, multiple bits can be determined to consume only fewer clock cycles using nodes represented by the information bits and frozen bits. The nodes called shared nodes in this paper. There are two combined nodes with similar bit patterns for hardware efficiency and one node with the rest bits grouped into 8 bits for fast multibit decision. In addition, a short-tailed sorter is proposed to reduce the critical path delay. As a large number of path metrics cause sorter delays, the proposed sorter can achieve high throughput with a small area. The proposed (1024, 512) SCL decoder showed negligible performance degradation in the simulation and was synthesized using 65 nm CMOS technology. The proposed decoder achieves about 1.3Gbps with a small area. As a result, area-throughput efficiency is the best among decoders above 1Gbps.
