This paper presents a high throughput and area efficient FFT processor for MIMO-OFDM systems based on the multi-path delay commutator (MDC) architecture. This paper proposes new scheduling schemes for reducing the number of complex multipliers and complex constant multipliers. In addition, this paper also proposes a novel structure of the complex constant multiplier which can be implemented without ROM and reduce the hardware complexity. The proposed MDC FFT processors can support 256, 128 and 64-point FFTs. The proposed processors have been designed and implemented with 90-nm CMOS technology. The proposed processors having eight-parallel data paths can achieve a high throughput rate up to 2.4 GS/s at 300 MHz.
