Low-density parity-check (LDPC) codes are one of the block coding techniques that can approach the Shannon’s limit within a fraction of a decibel for high block lengths. Recently, LDPC codes have been chosen to be part of many digital communication systems such as IEEE 802.11ad, IEEE 802.15.3c, and 5G telecommunications standard. As the standards are used to provide multi-Gbps throughput in mobile and portable computing devices, the codes allow effective hardware implementation and simultaneously achieve multi-Gbps decoding. The first two minimum values generator is the most complex module of LDPC decoder. This thesis introduces two low-complexity generators. The proposed bit-serial generator reduces the hardware complexity by approximately 26% compared with the existing bit-serial generator. Since the proposed generator requires long latency, a LDPC decoder using the bit-serial scheme is not suitable for multi-Gbps throughput. To achieve short latency, a bitwise generator is proposed, which is constructed using serially connected w bit-serial generators, where w is the word length. The bitwise generator takes only one clock cycle, reducing the hardware complexity by 15%. As the case studies, I have designed two LDPC decoders, flooding and layered schemes, based on a bitwise generator for the 802.11ad standard with the 90-nm CMOS technology. Compared to conventional decoders for 802.11ad, the decoders achieve the most efficient throughput-area ratio.
