An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory - Lee, Hayoung; Lee, Juyong; Kang, Sungho (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024)
With the rapid advances in artificial intelligence (AI), the demand for data-intensive analytics has surged. Consequently, extensive research on AI acceleration has been conducted to enhance AI performance. Processing-in-memory (PiM) has emerged as a promising AI acceleration architecture, offering an unprecedented high-bandwidth connection between compute and memory. However, integrating many components in PiM can lead to yield degradation. To address this issue, we propose an efficient test architecture that utilizes a hybrid built-in self-test (BIST) for PiM. This architecture utilizes the structural and operational characteristics of PiM to facilitate testing. It can execute testing through the existing functional paths without requiring any additional hardware implementation in PiM. Furthermore, it achieves a 100% test coverage with the small number of test patterns. In addition, the functionality of self-test can be realized for PiM through reconfiguration of the existing hardware, resulting in a very small area overhead.
Keywords: Area overhead; Artificial intelligence; Build in self tests; Build-in self-test; Builtin self tests (BIST); Data intensive; Processing-in-memory; Test architecture; Test-coverage; Area overhead; artificial intelligence (AI); built-in self-test (BIST); processing-in-memory (PiM); test coverage