A Robust Test Architecture for Low-Power AI Accelerators - Lee, Hayoung; Lee, Juyong; Kang, Sungho (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024)
With the rapid advancement of artificial intelligence (AI), there has been extensive research on AI accelerators to meet the demand for data-intensive analytics. Recently, low-power AI accelerators have been also developed to support battery-operated edge devices and minimize power consumption. However, traditional test architectures are insufficient for effectively testing such low-power AI accelerators. To address this issue, a robust test architecture for low-power AI accelerators has been proposed in this paper. The proposed test architecture employs a simple clock-gating technique in systolic array-based low-power AI accelerators and conducts testing through their functional paths. Accordingly, it can achieve 100 test coverage for both stuck-at and transition-delay faults with a minimal number of test patterns. Additionally, the proposed test architecture requires negligible area overhead since only one AND gate is implemented for the entire systolic array in low-power AI accelerators.
Keywords: Area overhead; Artificial intelligence; Data intensive; Low Power; Lowpower artificial intelligence accelerator; Power; Robust tests; Test architecture; Test-coverage; Toggle ratio; area overhead; Artificial intelligence (AI); lowpower AI accelerator; power consumption; systolic array; test coverage; toggle ratio