Effective Parallel Redundancy Analysis Using GPU for Memory Repair - Shin, Seung Ho; Lee, Hayoung; Kang, Sungho (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025)
The rapid increment of the memory density leads to an increment of fault occurrence in memory cells. To improve the memory yield, effective memory test and repair methodologies for automatic test equipment (ATE) have been studied. Multiple memory chips are tested simultaneously by the ATE to improve throughput and reduce costs. In general, redundancy analysis (RA) is used for memory repair. However, since conventional RA methods store fault information in the respective failure bitmaps and operate sequentially, those have limitations due to the high area and analysis time. To address these problems, a novel graphic processing unit (GPU)-based RA method has been proposed which significantly enhances the efficiency of searching for repair solutions for multiple memories. The proposed RA method strategically focuses on the pivot line to efficiently utilize parallel processing and reduce the solution search space. Moreover, the proposed method does not require the extensive use of failure bitmaps since all process is conducted on the GPU. The process involves real-time fault collection, analysis, spare allocation, and solution decision process dynamically during the memory test. Experimental results demonstrate that the performance of the proposed RA method achieves an optimal repair rate and high analysis speed for multiple memories.
Keywords: Analysis method; Automatic test equipment; Graphic processing unit; Graphics processing; Parallel processing; Processing units; Redundancy analysis; Redundancy analyze; Thread; Automatic test equipment (ATE); graphic processing unit (GPU); parallel processing; redundancy analysis (RA); thread