A DLL based clock multiplier using rotational DCDL and PRNG for spur reduction - Noh, Jinseop; Jee, Dong Woo (IEICE Electronics Express, 2019)
This paper presents a DLL based clock multiplier with a novel spur reduction technique. By randomly selecting delay line with pseudo random number generator (PRNG), the proposed scheme reduces the output spur due to delay cell mismatches. Rotational digitally controlled delay line (DCDL) is also proposed for seamless generation of clock edges even at random delay line switching. The clock multiplier is designed in 0.18µm CMOS process and achieves 5~11 dB reduction of spur while consuming 169.4µW for 16 MHz. The core area is 0.608mm 2 .
Keywords: Clock multipliers; CMOS processs; Digital DLL; Digitally controlled; Line switching; PRNG; Pseudo random number generators; Reduction techniques; Clock multiplier; Digital dll; DLL; PRNG; Spur reduction