Three-Dimensional Silicon Electronic Systems Fabricated by Compressive Buckling Process - Kim, Bong Hoon; Lee, Jungyup; Won, Sang Min; Xie, Zhaoqian; Chang, Jan Kai; Yu, Yongjoon; Cho, Youn Kyoung; Jang, Hokyung; Jeong, Ji Yoon; Lee, Yechan; Ryu, Arin; Kim, Do Hoon; et al. (ACS Nano, 2018)
Recently developed approaches in deterministic assembly allow for controlled, geometric transformation of two-dimensional structures into complex, engineered three-dimensional layouts. Attractive features include applicability to wide ranging layout designs and dimensions along with the capacity to integrate planar thin film materials and device layouts. The work reported here establishes further capabilities for directly embedding high-performance electronic devices into the resultant 3D constructs based on silicon nanomembranes (Si NMs) as the active materials in custom devices or microscale components released from commercial wafer sources. Systematic experimental studies and theoretical analysis illustrate the key ideas through varied 3D architectures, from interconnected bridges and coils to extended chiral structures, each of which embed n-channel Si NM MOSFETs (nMOS), Si NM diodes, and p-channel silicon MOSFETs (pMOS). Examples in stretchable/deformable systems highlight additional features of these platforms. These strategies are immediately applicable to other wide-ranging classes of materials and device technologies that can be rendered in two-dimensional layouts, from systems for energy storage, to photovoltaics, optoelectronics, and others.
Keywords: Geometric transformations; Micro-scale components; Silicon diodes; Silicon nanomembranes; Silicon transistors; Three-dimensional layout; Two-dimensional layout; Two-dimensional structures; Electronics; Finite Element Analysis; Lighting; Mechanical Phenomena; Metals; Nanostructures; Oxides; Silicon; Silicon Dioxide; mechanical buckling; silicon diode; silicon transistor; three-dimensional electronics